NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 505
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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SATA Controller Registers (D31:F2)
12.2.3
12.2.3.1
Intel
®
ICH8 Family Datasheet
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h
Default Value:
PxSSTS—Serial ATA Status Register (D31:F5)
Address Offset: BAR + 00h
Default Value:
This is a 32-bit register that conveys the current state of the interface and host. The
ICH8 updates it continuously and asynchronously. When the ICH8 transmits a
COMRESET to the device, this register is updated to its reset values.
31:12
31:2
1:0
Bit
Bit
Reserved
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
Table must be dword-aligned. The Descriptor Table must not cross a 64-KB boundary in
memory.
Reserved
Secondary: BAR + 0Ch
All bits undefined
00000000h
–
Description
0Fh
Description
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
RO
32 bits
505
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