NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 490
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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12.1.36
.
12.1.37
.
12.1.38
.
490
SCLKGC—SATA Clock General Configuration Register
Address Offset: 9Ch
Default Value:
SIRI—SATA Indexed Registers Index Register
Address Offset: A0h
Default Value:
STRD—SATA Indexed Register Data Register
Address Offset: A4h
Default Value:
31:0
7:2
1:0
Bit
Bit
7:2
Bit
1
0
Index (IDX) — R/W. This field is a 5-bit index pointer into the SATA Indexed Register
space. Data is written into and read from the SIRD register (D31:F2:A4h).
Reserved
Data (DTA) — R/W. 32-bit data value that is written to the register pointed to by SIRI
(D31:F2;A0h) or read from the register pointed to by SIRI.
Reserved
SATA2-port Configuration Indicator (SATA2PIND) — RO.
0 = Normal configuration.
1 = One IDE Controller is implemented supporting only two ports for a Primary
NOTE: When set, BIOS must ensure that bit 2 and bit 3 of the AHCI PI registers are
SATA4-port All Master Configuration Indicator (SATA4PMIND) — RO.
0 = Normal configuration.
1 = Two IDE Controllers are implemented, each supporting only two ports for a
NOTE: When set, BIOS must ensure that bit 2 and bit 3 of the AHCI PI registers are
Master and a Secondary Master.
Primary Master and a Secondary Master.
zeros. BIOS must also make sure that Port 2 and Port 3 are disabled (via PCS
configuration register) and the port clocks are gated (via SCLKCG
configuration register).
zeros. BIOS must also make sure that Port 2 and Port 3 are disabled (via PCS
configuration register) and the port clocks are gated (via SCLKCG
configuration register).
00h
00h
XXXXXXXXh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W
8 bits
R/W
8 bits
R/W
32 bits
Intel
®
ICH8 Family Datasheet
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