NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 186
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 186 of 890
- Download datasheet (7Mb)
.
Table 77.
Table 78.
186
TCO Legacy/Compatible Mode SMBus Configuration
In TCO Legacy/Compatible mode the Intel ICH8/ICH8M can function directly with the
integrated Gigabit Ethernet controller or equivalent external LAN controller to report
messages to a network management console without the aid of the system processor.
This is crucial in cases where the processor is malfunctioning or cannot function due to
being in a low-power state.
to the network management console.
Event Transitions that Cause Messages
NOTE: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the
INTRUDER# pin
THRM# pin
Watchdog Timer
Expired
GPIO[11]/
SMBALERT# pin
BATLOW#
CPU_PWR_FLR
GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
Event
Host SMBus
Controller 2
Controller 1
TCO Slave
Intel
Intel
Intel
SMBus
SMBus
®
®
®
Assertion?
ICH8
AMT
AMT
yes
yes
yes
yes
yes
yes
Table 78
X
X
SMLink
SMBus
Deassertion?
includes a list of events that will report messages
no (NA)
TCO Compatible Mode
yes
yes
yes
no
no
(Slave)
SPD
(Master or
Slave with
Sensors
ALERT)
Legacy
Must be in “S1 or hung S0” state
Must be in “S1 or hung S0” state. Note
that the THRM# pin is isolated when
the core power is off, thus preventing
this event in S3-S5.
“S1 or hung S0” state entered
Must be in “S1 or hung S0” state
Must be in “S1 or hung S0” state
“S1 or hung S0” state entered
uCtrl
Comments
Intel
(Master or
Sensors
Slave)
ASF
®
Functional Description
ICH8 Family Datasheet
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