NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 720

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

18.1.34
18.1.35
720
RCTL—Root Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 5Ch
Default Value:
RSTS—Root Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 60h
Default Value:
31:18
15:4
15:0
Bit
Bit
17
16
3
2
1
0
Reserved
PME Interrupt Enable (PIE) — R/W.
0 = Disable. Interrupt generation disabled.
1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/
System Error on Fatal Error Enable (SFE) — R/W.
0 = An SERR# will Not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit
System Error on Non-Fatal Error Enable (SNE) — R/W.
0 = An SERR# will Not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit
System Error on Correctable Error Enable (SCE) — R/W.
0 = An SERR# will Not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit
Reserved
PME Pending (PP) — RO.
0 = When the original PME is cleared by software, it will be set again, the requestor ID
1 = Another PME is pending when the PME status bit is set.
PME Status (PS) — R/WC.
0 = PME was not asserted.
1 = PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending
PME Requestor ID (RID) — RO. This field indicates the PCI requestor ID of the last
PME requestor. Valid only when PS is set.
F5:60h, bit 16) is in a set state (either due to a 0-to-1 transition, or due to this bit
being set with RSTS.IS already set).
8) is set, if a fatal error is reported by any of the devices in the hierarchy of this
root port, including fatal errors in this root port.
8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of
this root port, including non-fatal errors in this root port.
8) if a correctable error is reported by any of the devices in the hierarchy of this
root port, including correctable errors in this root port.
will be updated, and this bit will be cleared.
until this bit is cleared.
0000h
00000000h
–
–
63h
5Dh
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
R/W
16 bits
R/WC, RO
32 bits
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®
ICH8 Family Datasheet