NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 106

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Table 36.
106
SMBALERT# / GPIO11
HDA_SDIN[3:0]
Signal Name
LAN100_SLP
INTRUDER#
INTVRMEN
BATLOW#
SPI_MISO
RTCRST#
A20GATE
Power Plane for Input Signals for Mobile Configurations (Sheet 3 of 3)
FERR#
RCIN#
NOTE:
1.
2.
3.
CLK14
CLK48
TP[3]
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled
glitch free immediately after Reset until the time they are initialized as GPIO.
These signals can be configured as outputs in GPIO mode.
or low if it is disabled.
GPIO50, GPIO52, GPIO54 need to be glitch free immediately after Reset to when they are
being initialized to GPIO. Multiplexed GPIO signals defaulting to a native function must be
1
Suspend
Suspend
Suspend
Suspend
Suspend
Power
Well
Core
Core
Core
Core
Core
RTC
RTC
RTC
RTC
Intel
System Management Interface
®
High Definition Audio Interface
Driver During Reset
Miscellaneous Signals
Intel
Processor Interface
External RC Circuit
Clock Generator
Clock Generator
External Pull-up
External Pull-up
External Pull-up
SMBus Interface
External Switch
Internal Pull-up
InternalPull-up
Microcontroller
Microcontroller
Power Supply
®
Audio Codec
SPI Interface
Processor
External
External
High Definition
Clocks
§ §
Running
Running
C3/C4
Driven
Driven
Driven
Driven
Static
Static
High
High
High
High
High
High
Running
Running
Driven
Driven
Driven
Driven
Static
Static
High
High
High
High
High
Low
S1
Intel
®
Intel
ICH8 Family Datasheet
Driven
Driven
High
High
High
High
High
High
Low
®
Off
S3
Off
Off
Off
Off
ICH8 Pin States
S4/S5
Driven
Driven
High
High
High
High
High
High
Low
Off
Off
Off
Off
Off