NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 727

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
18.1.46
Intel
®
ICH8 Family Datasheet
SMSCS—SMI/SCI Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: DCh
Default Value:
29:5
Bit
31
30
4
3
2
1
0
Power Management SCI Status (PMCS) — R/WC. This bit is set if the PME control
logic needs to generate an interrupt, and this interrupt has been routed to generate an
SCI.
Hot Plug SCI Status (HPCS) — R/WC. This bit is set if the Hot-Plug controller needs
to generate an interrupt, and has this interrupt been routed to generate an SCI.
Reserved
Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC. This bit is set
when SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5:5A, bit 8) transitions from 0-to-1, and
MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will
be generated.
Hot Plug Command Completed SMI Status (HPCCM) — R/WC. This bit is set when
SLSTS.CC (D28:F0/F1/F2/F3/F4/F5:5A, bit 4) transitions from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be
generated.
Hot Plug Attention Button SMI Status (HPABM) — R/WC. This bit is set when
SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5:5A, bit 0) transitions from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be
generated.
Hot Plug Presence Detect SMI Status (HPPDM) — R/WC. This bit is set when
SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5:5A, bit 3) transitions from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be
generated.
Power Management SMI Status (PMMS) — R/WC. This bit is set when RSTS.PS
(D28:F0/F1/F2/F3/F4/F5:60, bit 16) transitions from 0-to-1, and MPC.PMME (D28:F0/
F1/F2/F3/F4/F5:D8, bit 1) is set.
00000000h
–
DFh
Description
Attribute:
Size:
R/WC
32 bits
727