NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 590
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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15.1.9
15.1.10
15.1.11
590
PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 0Dh
Default Value:
MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 10h
Default Value:
SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 2Ch
Default Value:
Reset:
31:10
15:0
7:0
Bit
9:4
2:1
Bit
Bit
3
0
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI
controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
Reserved
Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere
within 32-bit address space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address
field in this register maps to memory space.
Subsystem Vendor ID (SVID) — R/W (special). This register, in combination with the
USB 2.0 Subsystem ID register, enables the operating system to distinguish each
subsystem from the others.
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7,
D26:F7:80h, bit 0) is set to 1.
00h
00000000h
XXXXh
None
–
–
13h
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
RO
8 bits
R/W, RO
32 bits
R/W (special)
16 bits
Intel
®
ICH8 Family Datasheet
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