NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 359
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 359 of 890
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
9.4.5
9.4.6
Intel
®
ICH8 Family Datasheet
ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)
Offset Address: A1h
Default Value:
ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller
Default Value:
7:3
2:0
7:5
Bit
Bit
4
3
2
1
0
0 = These bits must be programmed to 0.
Slave Identification Code — WO. These bits are compared against the slave
identification code broadcast by the master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits
must be programmed to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the INTA# sequence, the slave
controller assumes responsibility for broadcasting the interrupt vector.
0 = These bits must be programmed to 0.
Special Fully Nested Mode (SFNM) — WO.
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for the ICH8. This is non-buffered mode.
Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI) — WO.
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
All bits undefined
Slave Controller
01h
–
–
0A1h
021h
Description
Description
Attribute:
Size:
Attribute:
Size:
WO
8 bits
WO
8 bits
359
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