NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 518

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

12.4.1.5
12.4.1.6
518
VS—AHCI Version (D31:F2)
Address Offset: ABAR + 10h–13h
Default Value:
This register indicates the major and minor version of the AHCI specification. It is BCD
encoded. The upper two bytes represent the major version number, and the lower two
bytes represent the minor version number. Example: Version 3.12 would be
represented as 00030102h. The current version of the specification is 1.10
(00010100h).
CCC_CTL—Command Completion Coalescing Control Register (D31:F2)
Address Offset: ABAR + 14h–17h
Default Value:
This register is used to configure the command coalescing feature. This register is
reserved if command coalescing is not supported (CAP_CCCS = ‘0’).
31:16
31:16
15:0
15:8
7:3
2:1
Bit
Bit
0
Major Version Number (MJR) — RO. Indicates the major version is 1
Minor Version Number (MNR) — RO. Indicates the minor version is 10.
Timeout Value (TV) — R/W. The timeout value is specified in 10 microsecond
intervals. hbaCCC_Timer is loaded with this timeout value. hbaCCC_Timer is only
decremented when commands are outstanding on the selected ports. The HBA will
signal a CCC interrupt when hbaCCC_Timer has decremented to ‘0’. The
hbaCCC_Timer is reset to the timeout value on the assertion of each CCC interrupt. A
timeout value of’0’ is invalid.
Command Completions (CC) — R/W. Specifies the number of command
completions that are necessary to cause a CCC interrupt. The HBA has an internal
command completion counter, hbaCCC_CommandsComplete.
hbaCCC_CommandsComplete is incremented by one each time a selected port has a
command completion. When hbaCCC_CommandsComplete is equal to the command
completions value, a CCC interrupt is signaled. The internal command completion
counter is reset to ‘0’ on the assertion of each CCC interrupt.
Interrupt (INT) — RO. Specifies the interrupt used by the CCC feature. This
interrupt must be marked as unused in the AHCI Ports Implemented memory register
by the corresponding bit being set to ‘0’. Thus, the CCC_interrupt corresponds to the
interrupt for an unimplemented port on the controller. When a CCC interrupt occurs,
the IS[INT] bit shall be asserted to ‘1’ regardless of whether PIRQ interrupt or MSI is
used.
For desktop INT is always 6.
Note that in MSI, CC interrupt may share an interrupt vector with other ports. For
example, if the number of message allocated is 4, then CCC interrupt share interrupt
vector 3 along with port 3, 4, and 5 but IS[6] shall get set.
Reserved
Enable (EN) — R/W.
0 = The command completion coalescing feature is disabled and no CCC interrupts are
1 = The command completion coalescing feature is enabled and CCC interrupts may
Software shall only change the contents of the TV and CC fields when EN is cleared to '0'. On
transition of this bit from '0' to '1', any updated values for the TV and CC fields shall take effect.
generated
be generated based on timeout or command completion conditions.
00010100h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
RO
32 bits
R/W, RO
32 bits
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