NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 650

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

17.1.14
17.1.15
T
17.1.16
650
SVID—Subsystem Vendor Identification Register
(Intel
Address Offset: 2Ch–2Dh
Default Value:
The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
SID—Subsystem Identification Register
(Intel
Address Offset: 2Eh
Default Value:
The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch)
make it possible for the operating environment to distinguish one audio subsystem
from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
CAPPTR—Capabilities Pointer Register (Audio—D30:F2)
Address Offset: 34h
Default Value:
This register indicates the offset for the capability pointer.
15:0
15:0
Bit
7:0
Bit
Bit
Subsystem Vendor ID — R/WO.
®
®
Subsystem ID — R/WO.
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer
offset is offset 50h (Power Management Capability)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
0000h
0000h
50h
–
2Fh
Intel
HOT
HOT
®
Description
Description
Description
to D0 transition.
to D0 transition.
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/WO
16 bits
R/WO
16 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet