NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 395
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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Compliant
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LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet
(Mobile
Only)
Bit
3:1
4
0
Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI
or SMI#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by the ICH8 when a bus master requests access to main memory. Bus
NOTES:
1.
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are
master activity is detected by any of the PCI Requests being active, any internal
bus master request being active, the BMBUSY# signal being active, or REQ-C2
message received while in C3 or C4 state.
numbered from 0 to 23). This will occur every 2.3435 seconds. When the
TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS
bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0.
LPC DMA and bus master activity will always set the BM_STS bit, even if the
BM_STS_ZERO_EN bit is set.
Description
395
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