NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 322

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
8.2.4
8.2.5
322
EXTCNF_CTRL—Extended Configuration Control Register
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: GBAR0 + F00h
Default Value:
LDR2—LAN Device Initialization Register 2
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: GBAR0 + 3004h
Default Value:
31:10
19:16
31:6
15:0
4:0
Bit
Bit
5
Reserved
SW Semaphore Flag (SWFLAG) — R/W. This bit is set by the device driver to gain
access permission to shared CSR registers with the firmware and hardware
Reserved
Reserved
LDR2 Field 1 — R/W. BIOS must program this field to 0101b.
Reserved
000000002h
B2B47CCh
§ §
Description
Description
Attribute:
Size:
Attribute:
Size:
Gigabit LAN Configuration Registers
R/W, RO
32 bits
R/W
32 bits
Intel
®
ICH8 Family Datasheet

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