NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 733

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
18.1.57
Intel
®
ICH8 Family Datasheet
31:21
11:5
UEM — Uncorrectable Error Mask
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 148h
Default Value:
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
3:1
Bit
20
19
18
17
16
15
14
13
12
4
0
Reserved
Unsupported Request Error Mask (URE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
ECRC Error Mask (EE) — RO. ECRC is not supported.
Malformed TLP Mask (MT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Receiver Overflow Mask (RO) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Unexpected Completion Mask (UC) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Completion Abort Mask (CA) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Completion Timeout Mask (CT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not
supported.
Poisoned TLP Mask (PT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Reserved
Data Link Protocol Error Mask (DLPE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked.
Reserved
Training Error Mask (TE) — RO. Training Errors not supported
00000000h
–
14Bh
Description
Attribute:
Size:
R/WO, RO
32 bits
733