NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 643
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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Compliant
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Intel
17
Note:
Note:
17.1
Note:
Table 139.
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
Intel
Controller Registers (D27:F0)
The Intel High Definition Audio controller resides in PCI Device 27, Function 0 on bus 0.
This function contains a set of DMA engines that are used to move samples of digitally
encoded data between system memory and external codecs.
All registers in this function (including memory-mapped registers) must be addressable
in byte, word, and DWord quantities. The software must always make register accesses
on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word
accesses on word boundaries, etc.) In addition, the memory-mapped register space
must not be accessed with the LOCK semantic exclusive-access mechanism. If software
attempts exclusive-access mechanisms to the Intel High Definition Audio memory-
mapped space, the results are undefined.
Users interested in providing feedback on the Intel High Definition Audio specification
or planning to implement the Intel High Definition Audio specification into a future
product will need to execute the Intel
Agreement. For more information, contact nextgenaudio@intel.com.
Intel
Space (Intel
Address locations that are not shown should be treated as Reserved.
Intel
(Intel
2Ch–2Dh
00h–01h
02h–03h
04h–05h
06h–07h
10h–13h
14h–17h
Offset
0Ah
0Bh
0Ch
0Dh
08h
09h
0Eh
®
®
High Definition Audio PCI Register Address Map
®
High Definition Audio D27:F0)
High Definition Audio PCI Configuration
®
Mnemonic
HEADTYP
HDBARU
HDBARL
PCICMD
PCISTS
SVID
SCC
BCC
DID
RID
CLS
VID
PI
LT
High Definition Audio
®
High Definition Audio— D27:F0)
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Latency Timer
Header Type
Intel
Address (Memory)
Intel High Definition Audio Upper Base
Address (Memory)
Subsystem Vendor Identification
®
High Definition Audio Lower Base
Register Name
®
High Definition Audio Specification Developer’s
See register
See register
00000004h
00000000h
description
description
Default
8086h
0000h
0010h
0000h
00h
03h
04h
00h
00h
00h
R/WC, RO
R/W, RO
R/W, RO
Access
R/WO
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
643
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