NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 604
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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15.2.1.1
15.2.1.2
604
CAPLENGTH—Capability Registers Length
Offset:
Default Value:
HCIVERSION—Host Controller Interface Version Number
Offset:
Default Value:
15:0
7:0
Bit
Bit
Capability Register Length Value — RO. This register is used as an offset to add to the
Memory Base Register (D29:F7, D26:F7:10h) to find the beginning of the Operational
Register Space. This field is hardwired to 20h indicating that the Operation Registers
begin at offset 20h.
Host Controller Interface Version Number — RO. This is a two-byte register containing a
BCD encoding of the version number of interface that this host controller interface
conforms.
MEM_BASE + 00h
20h
MEM_BASE + 02h
0100h
–
03h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
RO
8 bits
RO
16 bits
Intel
®
ICH8 Family Datasheet
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