NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 419

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.9.5
Intel
®
ICH8 Family Datasheet
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
15:6
Bit
5
4
3
2
1
Reserved
ME_WAKE_STS — R/WC. This bit is set when the ME generates a Non-Maskable wake
event, and is not affected by any other enable bit. When this bit is set, the Host Power
Management logic wakes to S0.
This bit is only set by hardware and can only be reset by writing a one to this bit
position. This bit is not affected by hard resets caused by a CF9 write, but is reset by
RSMRST.
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to
go directly into pre-determined sleep state. This avoids race conditions. Software clears
this bit by writing a 1 to it.
0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit
1 = ICH8 sets this bit to 1 when it receives the SMI message on the SMLink's Slave
Reserved
BOOT_STS — R/WC.
0 = Cleared by ICH8 based on RSMRST# or by software writing a 1 to this bit. Note
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the
ICH8 will reboot using the ‘safe’ multiplier (1111). This allows the system to recover
from a processor frequency multiplier that is too high, and allows the BIOS to check the
BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the
BIOS knows that the processor has been programmed to an invalid multiplier.
SECOND_TO_STS — R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = ICH8 sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently)
from S3–S5 states.
Interface.
that software should first clear the SECOND_TO_STS bit before writing a 1 to clear
the BOOT_STS bit.
fetched the first instruction.
set and a second timeout occurred before the TCO_RLD register was written. If this
bit is set and the NO_REBOOT config bit is 0, then the ICH8 will reboot the system
after the second timeout. The reboot is done by asserting PLTRST#.
TCOBASE +06h
0000h
No
Description
Attribute:
Size:
Power Well:
R/W, R/WC
16-bit
Resume
(Except Bit 0, in RTC)
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