NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 697

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
PCI Express* Configuration Registers
18
18.1
Note:
/
Table 141.
Intel
®
ICH8 Family Datasheet
PCI Express* Configuration
Registers
PCI Express* Configuration Registers
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Register address locations that are not shown in
Reserved.
PCI Express* Configuration Registers Address Map
(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 1 of 3)
1Ch–1Dh
3Ch–3Dh
00h–01h
02h–03h
04h–05h
06h–07h
18h–1Ah
20h–23h
24h–27h
28h–2Bh
2Ch–2Fh
40h–41h
1Eh–1Fh
3Eh–3Fh
Offset
0Ah
0Bh
0Ch
0Dh
1Bh
08h
09h
0Eh
34h
Mnemonic
HEADTYP
PMBU32
PCICMD
PMLU32
PCISTS
BCTRL
BNUM
CLIST
SSTS
PMBL
CAPP
INTR
IOBL
SCC
BCC
MBL
VID
DID
RID
CLS
SLT
PLT
PI
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Primary Latency Timer
Header Type
Bus Number
Secondary Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and
Limit
Prefetchable Memory Base Upper
32 Bits
Prefetchable Memory Limit Upper
32 Bits
Capabilities List Pointer
Interrupt Information
Bridge Control Register
Capabilities List
Register Name
Table 141
and should be treated as
Function 0–5
See register
See register
00000000h
00010001h
00000000h
00000000h
description
description
description
000000h
Default
See bit
8086h
0000h
0010h
0000h
0000h
0000h
8010
00h
00h
81h
00h
04h
06h
40h
0h
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WC
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
697

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