NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 339

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet
5:4
Bit
12
11
10
9
8
7
6
3
FWH_E0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FWH_D8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_D0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_C8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_C0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at
F0000h – FFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
FWH_Legacy_E_EN — R/W. This enables the decoding of the legacy 128-K range at
E0000h – EFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
Reserved
FWH_70_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFE00000h – FFE7FFFFh
FFA00000h – FFA7FFFFh
FFD80000h – FFDFFFFFh
FF980000h – FF9FFFFFh
FFD00000h – FFD7FFFFh
FF900000h – FF97FFFFh
FFC80000h – FFCFFFFFh
FF880000h – FF8FFFFFh
FFC00000h – FFC7FFFFh
FF800000h – FF87FFFFh
F0000h – FFFFFh
E0000h – EFFFFh
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
Description
339

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