NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 591
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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EHCI Controller Registers (D29:F7, D26:F7)
15.1.12
15.1.13
15.1.14
15.1.15
Intel
®
ICH8 Family Datasheet
SID—USB EHCI Subsystem ID Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 2Eh
Default Value:
Reset:
CAP_PTR—Capabilities Pointer Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 34h
Default Value:
INT_LN—Interrupt Line Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 3Dh
Default Value:
15:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the
USB 2.0 capabilities ranges.
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
as a scratchpad register to communicate to software the interrupt line that the
interrupt pin is connected to.
Interrupt Pin — RO. This reflects the value of D29IP.EIP (Chipset Config
Registers:Offset 3108:bits 31:28) or D26IP.EIP (Chipset Config Registers:Offset
3114:bits 31:28).
NOTE: Bits 7:4 are always 0h
Subsystem ID (SID) — R/W (special). BIOS sets the value in this register to identify
the Subsystem ID. This register, in combination with the Subsystem Vendor ID register,
enables the operating system to distinguish each subsystem from other(s).
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7,
D26:F7:80h, bit 0) is set to 1.
XXXXh
None
50h
00h
See Description
–
2Fh
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W (special)
16 bits
RO
8 bits
R/W
8 bits
RO
8 bits
®
ICH8. It is used
591
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