NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 524

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

12.4.2.1
12.4.2.2
524
PxCLB—Port [5:0] Command List Base Address Register
(D31:F2)
Address Offset: Port 0: ABAR + 100h
Default Value:
PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 104h
Default Value:
31:10
31:0
9:0
Bit
Bit
Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
structure pointed to by this address range is 1 KB in length. This address must be 1-KB
aligned as indicated by bits 31:10 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved — RO
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
commands to execute.
Note that these bits are not reset on a HBA reset.
Port 1: ABAR + 180h
Port 2: ABAR + 200h
Port 3: ABAR + 280h (Desktop Only)
Port 4: ABAR + 300h (Desktop Only)
Port 5: ABAR + 380h (Desktop Only)
Undefined
Port 1: ABAR + 184h
Port 2: ABAR + 204h
Port 3: ABAR + 284h (Desktop Only)
Port 4: ABAR + 304h (Desktop Only)
Port 5: ABAR + 384h (Desktop Only)
Undefined
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W, RO
32 bits
R/W
32 bits
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ICH8 Family Datasheet