NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 385

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.1.6
Intel
®
ICH8 Family Datasheet
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile Only)
Offset Address: AAh
Default Value:
Lockable:
Power Well:
This register is used to enable C-state related modes.
5:4
3:2
1:0
Bit
7
6
Reserved
Slow-C4 Exit Enable —When 1, this bit enables the Slow-C4 Exit functionality.
Slow-C4 Exit Delay. This field selects the amount of time that the ICH8 waits from
deassertion of DPRSTP# until starting the t266 timer when performing the Slow-C4
exit.
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the ICH8
waits for from the deassertion of DPRSLPVR to the deassertion of STP_CPU#. This
provides a programmable time for the processor’s voltage to stabilize when exiting
from a C4 state. Thus, thus changes the value for t266.
DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#
deassertion time (t270). Normally this value is determined by the
CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,
then the values in this register have higher priority. It is software’s responsibility to
program these fields in a consistent manner.
Bits
00b
01b
10b
11b
Bits
00b
01b
10b
11b
Bits
00b
01b
10b
11b
00h
No
Core
t266
73 µs
67 µs
61 µs
46 µs
t270
Use value is CPU_PLL_LOCK_TIME field (default is 30 µs)
20 µs
15 µs
10 µs
Min
95 µs
22 µs
34 µs
min
t266
101 µs
76 µs
70 µs
64 µs
49 µs
28 µs
40 µs
Max
max
Description
compatible with 10b setting of t266
compatible with 11b setting of t266
Comment
Default. compatible with 01b setting of
t266
Comment
Default
Value used for “Fast” VRMs
Value used for “Fast” VRMs
Reserved
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
385