NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 231

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 89.
Table 90.
Table 91.
Intel
Slave Write to Wake/
SMI# Command
Slave Write to
SMLINK_SLAVE_SMI
Command
Any combination of
Host Status Register
[4:1] asserted
SMBALERT#
asserted low
(always reported
in Host Status
Register, Bit 5)
Register, Offset 11h, bit 0)
HOST_NOTIFY_INTREN
®
(Slave Control I/O
ICH8 Family Datasheet
Event
Event
X
0
1
1
Enable for SMBALERT#
Enables for SMBus Slave Write and SMBus Host Events
Enables for the Host Notify Command
Register, Offset
INTREN (Host
Control I/O
02h, Bit 0)
Control I/O Register,
Offset 02h, Bit 0)
INTREN (Host
X
X
1
D31:F3:Off40h, Bit 1)
SMB_SMI_EN (Host
Config Register,
X
X
0
1
1
D31:F3:Offset 40h, Bit 1)
Configuration Register,
X
X
0
1
SMB_SMI_EN (Host
D31:F3:Offset 40h, Bit1)
Configuration Register,
SMB_SMI_EN (Host
X
1
0
Register, Offset 11h, bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
X
X
X
0
1
Offset 11h, Bit 2)
(Slave Command
SMBALERT_DIS
0
1
X
X
I/O Register,
Wake generated when asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
None
Interrupt generated
Host SMI# generated
X
0
0
None
Wake generated
Interrupt generated
Slave SMI# generated
(SMBUS_SMI_STS)
Event
Wake generated
Slave SMI#
generated
(SMBUS_SMI_STS)
Interrupt
generated
Result
Result
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