NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 351
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 351 of 890
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
9.2.10
9.2.11
Intel
®
ICH8 Family Datasheet
DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
7:0
7:4
3:0
Bit
Bit
Clear Mask Register — WO. No specific pattern. Command enabled with a write to the
port.
Reserved. Must be 0.
Channel Mask Bits — R/W. This register permits all four channels to be
simultaneously enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register – Write Single Mask Bit. In addition,
this register has a read path to allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register
reaches terminal count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0
enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master
Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)
Bit 1 = Channel 1 (5)
Bit 2 = Channel 2 (6)
Bit 3 = Channel 3 (7)
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channel’s
0 – 3 through channel 4.
Ch. #0
Ch. #4
xxxx xxxx
No
Ch. #0
Ch. #4
0000 1111
No
–
–
–
–
3 = 0Eh;
7 = DCh
3 = 0Fh;
7 = DEh
1 = Masked, 0 = Not Masked
1 = Masked, 0 = Not Masked
1 = Masked, 0 = Not Masked
1 = Masked, 0 = Not Masked
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
WO
8-bit
Core
R/W
8-bit
Core
351
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