NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 712

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

18.1.26
712
DCTL—Device Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 48h–49h
Default Value:
14:12
7:5
Bit
15
11
10
9
8
4
3
2
1
0
Reserved
Max Read Request Size (MRRS) — RO. Hardwired to 0.
Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-
snoop requests.
Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device
connected has detected aux power. It has no effect on the root port otherwise.
Phantom Functions Enable (PFE) — RO. Not supported.
Extended Tag Field Enable (ETFE) — RO. Not supported.
Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,
regardless of the programming of this field.
Enable Relaxed Ordering (ERO) — RO. Not supported.
Unsupported Request Reporting Enable (URE) — R/W.
0 = Disable. The root port will ignore unsupported request errors.
1 = Enable. Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root
Fatal Error Reporting Enable (FEE) — R/W.
0 = Disable. The root port will ignore fatal errors.
1 = Enables signaling of ERR_FATAL to the Root Control register due to internally
Non-Fatal Error Reporting Enable (NFE) — R/W.
0 = Disable. The root port will ignore non-fatal errors.
1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally
Correctable Error Reporting Enable (CEE) — R/W.
0 = Disable. The root port will ignore correctable errors.
1 = Enables signaling of ERR_CORR to the Root Control register due to internally
Control register when detecting an unmasked Unsupported Request (UR). An
ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an
uncorrectable non-Advisory UR is received with the severity set by the
Uncorrectable Error Severity register.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
0000h
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/W, RO
16 bits
Intel
®
ICH8 Family Datasheet