NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 515

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.4.1.2
Intel
®
ICH8 Family Datasheet
GHC—Global ICH8 Control Register (D31:F2)
Address Offset: ABAR + 04h–07h
Default Value:
30:3
Bit
31
2
1
0
AHCI Enable (AE) — R/W. When set, indicates that an AHCI driver is loaded and the
controller will be talked to via AHCI mechanisms. This can be used by an ICH8 that
supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the
controller will not be talked to as legacy.
0 = Software will only talk to the ICH8 using legacy mechanisms.
1 = Software will only talk to the ICH8 using AHCI. The ICH8 will not have to allow
Software shall set this bit to 1 before accessing other AHCI registers.
Reserved
MSI Revert to Single Message (MRSM) — RO: When set to 1 by hardware, indicates
that the host controller requested more than one MSI vector but has reverted to using
the first vector only. When this bit is cleared to '0', the HBA has not reverted to single
MSI mode (i.e. hardware is already in single MSI mode, software has allocated the
number of messages requested, or hardware is sharing interrupt vectors if MC.MME <
MC.MMC).
When this bit is set to '1', single MSI mode operation is in use and software is
responsible for clearing bits in the IS register to clear interrupts.
This bit shall be cleared to '0' by hardware when any of the four conditions stated is
false. This bit is also cleared to '0' when MC.MSIE = '1' and MC.MME = 0h. In this case,
the hardware has been programmed to use single MSI mode, and is not "reverting" to
that mode.
For ICH8, the HBA shall always revert to single MSI mode when the number of vectors
allocated by the host is less than the number requested.
Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH8.
0 = All interrupt sources from all ports are disabled.
1 = Interrupts are allowed from the AHCI controller.
HBA Reset (HR) — R/W. Resets ICH8 AHCI controller.
0 = No effect
1 = When set by SW, this bit causes an internal reset of the ICH8 AHCI controller. All
NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host
"MC.MSIE = '1' (MSI is enabled)
"MC.MMC > 0 (multiple messages requested)
"MC.MME > 0 (more than one message allocated)
"MC.MME != MC.MMC (messages allocated not equal to number requested)
command processing via both AHCI and legacy mechanisms.
state machines that relate to data transfers and queuing return to an idle condition,
and all ports are re-initialized via COMRESET.
Controller Interface specification.
00000000h
Description
Attribute:
Size:
R/W
32 bits
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