NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 504
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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12.2.2
504
BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
Address Offset: Primary: BAR + 02h
Default Value:
4:3
Bit
7
6
5
2
1
0
PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
Reserved. Returns 0.
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH8 when the last transfer for a region is performed,
1 = Set by the ICH8 when the Start bit is written to the Command register.
set.
drive 1 for this channel is capable of DMA transfers, and that the controller has been
initialized for optimum performance. The Intel
intended for systems that do not attach BMIDE to the PCI bus.
drive 0 for this channel is capable of DMA transfers, and that the controller has been
initialized for optimum performance. The ICH8 does not use this bit. It is intended
for systems that do not attach BMIDE to the PCI bus.
disabled interrupts via the IEN bit of the Device Control Register (see chapter 5 of
the Serial ATA Specification, Revision 2.5).
transferring data on PCI.
where EOT for that region is set in the region descriptor. It is also cleared by the
ICH8 when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
Secondary: BAR + 0Ah
00h
Description
Attribute:
Size:
®
ICH8 does not use this bit. It is
SATA Controller Registers (D31:F2)
R/W, R/WC, RO
8 bits
Intel
®
ICH8 Family Datasheet
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