NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 793

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Thermal Sensor Registers (D31:F6)
21.1.12
21.1.13
21.1.14
Intel
®
ICH8 Family Datasheet
BIST—Built-in Self Test
Address Offset: 0Fh
Default Value:
TBAR—Thermal Base
Address Offset: 10h
Default Value:
This BAR creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers. This memory space is active when the Command
(CMD) register Memory Space Enable (MSE) bit is set and either TBAR[31:12] or
TBARH are programmed to a non-zero address. This BAR is programmed by the
Operating System, and allows the OS to locate the Thermal registers in system
memory space.
TBARH—Thermal Base High DWord
Address Offset: 14h
Default Value:
This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR,
it creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers.
31:12
11:4
31:0
2:1
7:0
Bit
Bit
Bit
3
0
Thermal Base Address (TBA) — R/W. This field provides the base address for the
Thermal logic memory mapped configuration registers; 4 KB are requested by
hardwiring bits 11:4 to 0s.
Reserved
Prefetchable (PREF) — RO. This bit indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG) — RO. This field indicates that this BAR can be located
anywhere in 64 bit address space.
Space Type (SPTYP) — RO. This bit indicates that this BAR is located in memory
space.
Thermal Base Address High (TBAH) — R/W. TBAR bits 61:32.
Built-in Self Test (BIST) — RO. Not implemented. Hardwired to 00h.
00h
00000004h
00000000h
–
–
13h
17h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, RO
32 bits
R/W,RO
32 bits
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