NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 495
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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SATA Controller Registers (D31:F2)
12.1.49
.
12.1.50
.
12.1.51
.
12.1.52
.
Intel
®
ICH8 Family Datasheet
STTT3—SATA Indexed Registers Index 90h
(SATA TX Termination Test Register 3)
Address Offset: Index 90h - 93h
Default Value:
SIR94—SATA Indexed Registers Index 94h
(SATA Initialization Register 94h)
Address Offset: Index 94h - 97h
Default Value:
SIRA0—SATA Indexed Registers Index A0h
(SATA Initialization Register A0h)
Address Offset: Index A0h - A3h
Default Value:
SIRA8—SATA Indexed Registers Index A8h
(SATA Initialization Register A8h)
Address Offset: Index A8h - ABh
Default Value:
31:2
31:0
31:0
31:0
Bit
Bit
Bit
Bit
1
0
Reserved.
Port 5 TX Termination Test Enable — R/W:
0 = Port 1 TX termination port testing is disabled.
1 = Setting this bit will enable testing of Port 1 TX termination.
NOTE: This bit only to be used for system board testing.
Port 4 TX Termination Test Enable — R/W:
0 = Port 0 TX termination port testing is disabled.
1 = Setting this bit will enable testing of Port 0 TX termination.
NOTE: This bit only to be used for system board testing.
BIOS programs this field to 00000022h.
BIOS programs this field to 0000001Bh.
BIOS programs this field to 00240024h.
00000000h
00000011h
0000001Bh
002D0024h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W
32 bits
R/W
32 bits
R/W
32 bits
495
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