NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 394

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

394
(Desktop
Only)
7:6
Bit
11
10
9
8
5
4
Power Button Override Status (PRBTNOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (i.e., the power button is
RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8#
ME_STS: This bit is set when the ME generates a Non-Maskable wake event, and is
not affected by any other enable bit. When this bit is set, the Host Power
Management logic wakes to S0.
This bit is only set by hardware and can only be reset by writing a one to this bit
position. This bit is not affected by hard resets caused by a CF9 write, but is reset by
RSMRST#.
Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard
resets caused by a CF9 write.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low,
NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is
Reserved
Global Status (GBL _STS) — R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI
Reserved
pressed for at least 4 consecutive seconds), or due to the corresponding bit in
the SMBus slave message. The power button override causes an unconditional
transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI
handler clears this bit by writing a 1 to it. This bit is not affected by hard resets
via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved
through power failures. Note that if this bit is still asserted when the global
SCI_EN is set then an SCI will be generated.
signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting
of the RTC_STS bit will generate a wake event.
the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions
to the S5 state with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
independent of any other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or
SMI# if SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and
PWRBTN_STS are both set, a wake event is generated.
handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and
set this bit.
sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN#
signal must go inactive and active again to set the PWRBTN_STS bit.
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet