NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 156

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

5.12.1.2
Note:
Table 59.
156
INIT# (Initialization)
The INIT# signal is active (driven low) based on any one of several events described in
Table
driven high.
The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if
INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after
STPCLK# goes inactive.
This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#
(Desktop Only), as INIT3_3V# (Desktop Only) is functionally identical to INIT#, but
signaling at 3.3 V.
INIT# Going Active
Shutdown special cycle from processor observed
on ICH-GMCH interconnect (from GMCH).
PORT92 write, where INIT_NOW (bit 0) transitions
from a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0
and RST_CPU (bit 2) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected
to be driven by the external microcontroller
(KBC).
CPU BIST
59. When any of these events occur, INIT# is driven low for 16 PCI clocks, then
Cause of INIT# Going Active
INIT# assertion based on value of
Shutdown Policy Select register (SPS)
0 to 1 transition on RCIN# must occur
before the Intel
generated again.
NOTE: RCIN# signal is expected to be low
To enter BIST, software sets CPU_BIST_EN
bit and then does a full processor reset
using the CF9 register.
during S3, S4, and S5 states.
Transition on the RCIN# signal in
those states (or the transition to
those states) may not necessarily
cause the INIT# signal to be
generated to the processor.
®
Comment
ICH8 will arm INIT# to be
Intel
®
Functional Description
ICH8 Family Datasheet