NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 786

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

20.3.14
786
SSFC—Software Sequencing Flash Control Register
(
Memory Address:GLBAR + 91h
Default Value:
23:19
18:16
GbE LAN Memory Mapped Configuration Registers
13:8
6:4
Bit
15
14
7
3
2
1
0
Reserved
SPI Cycle Frequency (SCF): — R/W.
000 = 20 MHz
001 = 33 MHz
All other values reserved
Software should program this register to set the frequency of the cycle that is to be
run.
Reserved
Data Cycle (DS): — R/W. When set to 1, there is data that corresponds to this
transaction. When 0, no data is delivered for this cycle, and the DBC and data fields
themselves are do not cares
Data Byte Count (DBC): — R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
value from 0 to 3. The number of bytes transferred is the value of this field plus 1.
Note that when this field is 00b, then there is 1 byte to transfer and that 11b means
there are 4 bytes to transfer.
Reserved
Cycle Opcode Pointer (COP): — R/W. This field selects one of the programmed
opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an
Atomic Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer (SPOP): — R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A
value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
register. By making this programmable, the ICH8 supports flash devices that have
different opcodes for enabling writes to the data space vs. status register.
Atomic Cycle Sequence (ACS): — R/W. When set to 1 along with the SCGO
assertion, the ICH8 will execute a sequence of commands on the SPI interface without
allowing the LAN component to arbitrate and interleave cycles. The sequence is
composed of:
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset
until the Busy bit in the Flash Status Register returns 0.
SPI Cycle Go (SCGO): — R/WS. This bit always returns 0 on reads. However, a write
to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this
register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware must
ignore writes to this bit while the Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
Reserved
• Atomic Sequence Prefix Command (8-bit opcode only)
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
000000h
Description
Attribute:
Size:
Serial Peripheral Interface (SPI)
R/W
24 bits
)
Intel
®
ICH8 Family Datasheet