NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 399
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 399 of 890
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet
7:5
3:1
Bit
4
0
THRM_DTY — WO. This write-once field determines the duty cycle of the throttling
when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage
of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK#
throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in
the C0 state. For mobile components, if in the C2, C3, or C4 state, no throttling occurs.
Once the THRM_DTY field is written, any subsequent writes will have no effect until
PLTRST# goes active.
THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-
controlled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
THTL_DTY — R/W. This field determines the duty cycle of the throttling when the
THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle
period is 1024 PCICLKs.
Reserved
THRM_DTY
THTL_DTY
000b
001b
010b
011b
100b
101b
110b
111b
000b
001b
010b
011b
100b
101b
110b
111b
Throttle Mode
Throttle Mode
50% (Default)
50% (Default)
87.5%
75.0%
62.5%
37.5%
12.5%
87.5%
75.0%
62.5%
37.5%
12.5%
50%
25%
50%
25%
Description
PCI Clocks
PCI Clocks
512
896
768
640
512
384
256
128
512
896
768
640
512
384
256
128
399
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