NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 484

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

484
Bits
6:4
3:1
0
Multiple Message Enable (MME): When this field is cleared to ‘000’ (and MSIE is set),
only a single MSI message will be generated for all SATA ports, and bits [15:0] of the
message vector will be driven from MD[15:0].
When this field is set to ‘001’ (and MSIE is set), two MSI messages will be generated. Bit
[15:1] of the message vectors will be driven from MD[15:1] and bit [0] of the message
vector will be driven dependent on which SATA port is the source of the interrupt: ‘0’ for
port 0, and ‘1’ for ports 1, 2, 3, 4 and 5.
When this field is set to ‘010’ (and MSIE is set), four messages will be generated, one for
each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:2], while
bits[1:0] will be driven dependent on which SATA port is the source of the interrupt: ‘00’
for port 0, ‘01’ for port 1, ‘10’ for port 2, and ‘11’ for ports 3, 4, and 5).
When this field is set to ‘100’ (and MSIE is set), seven messages will be generated, one
for each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:3],
while bits[2:0] will be driven dependent on which SATA port is the source of the
interrupt: ‘000’ for port 0, ‘001’ for port 1, ‘010’ for port 2, ‘011’ for port 3, ‘100’ for port
4, ‘101 for port 5, and ‘110’ for port 6 (CCC interrupt).
.
Values ‘011b’ to ‘111b’ are reserved. If this field is set to one of these reserved values,
the results are undefined.
NOTE: Note: The CCC interrupt is generated on unimplemented port (AHCI PI register
Multiple Message Capable (MMC): Indicates the number of interrupt messages
supported by the ICH8 SATA controller.
000 = 1 MSI Capable (When CC.SCC bit is set to 01h. MSI is not supported in IDE mode)
010 = 4 MSI Capable
100 = 8 MSI Capable
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used to
generate interrupts. This bit is R/W when SC.SCC is not 01h and is read-only 0 when
CC.SCC is 01h. Note that CMD.ID bit has no effect on MSI.
NOTE: Software must clear this bit to ‘0’ to disable MSI first before changing the number
MME
000
001
010
100
bit equal to 0). If CCC interrupt is disabled, no MSI shall be generated for the port
dedicated to the CCC interrupt. When CCC interrupt occurs, MD[2:0] is
dependant on CCC_CTL.INT (in addition to MME).
of messages allocated in the MMC field. Software must also make sure this bit is
cleared to ‘0’ when operating in legacy mode (when GHC.AE = 0).
Bits[15:2]
MD[15:0]
MD[15:2]
MD[15:2]
MD[15:3]
Value Driven on MSI Memory Write
Port 0: 000
Port 1: 001
Port 2: 010
Port 3: 011
Port 4: 100
Port 5: 101
Port 0: 0
Port 1: 0
Port 2: 1
Port 3: 1
Bit[2]
MD[1]
MD[1]
Description
Port 0: 000
Port 1: 001
Port 2: 010
Port 3: 011
Port 4: 100
Port 5: 101
Port 0: 0
Port 1: 0
Port 2: 1
Port 3: 1
Bit[1]
MD[1]
MD[1]
SATA Controller Registers (D31:F2)
Ports 1,2,3: 1
Port 0: 000
Port 1: 001
Port 2: 010
Port 3: 011
Port 4: 100
Port 5: 101
Intel
Ports 0: 0
Port 0: 0
Port 1: 1
Port 2: 0
Port 3: 1
Bit[0]
MD[0]
®
ICH8 Family Datasheet