NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 533

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.4.2.10
Intel
®
ICH8 Family Datasheet
PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)
Address Offset: Port 0: ABAR + 128h
Default Value:
This is a 32-bit register that conveys the current state of the interface and host. The
ICH8 updates it continuously and asynchronously. When the ICH8 transmits a
COMRESET to the device, this register is updated to its reset values.
31:12
11:8
7:4
3:0
Bit
Reserved
Interface Power Management (IPM) — RO. Indicates the current interface state:
All other values reserved.
Current Interface Speed (SPD) — RO. Indicates the negotiated interface
communication speed.
All other values reserved.
ICH8 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0
Gb/s).
Device Detection (DET) — RO. Indicates the interface device detection and Phy
state:
All other values reserved.
Value
Value
Value
0h
1h
2h
6h
0h
1h
2h
0h
1h
3h
4h
Port 1: ABAR + 1A8h
Port 2: ABAR + 228h
Port 3: ABAR + 2A8h (Desktop Only)
Port 4: ABAR + 328h (Desktop Only)
Port 5: ABAR + 3A8h (Desktop Only)
00000000h
Description
Device not present or communication not established
Interface in active state
Interface in PARTIAL power management state
Interface in SLUMBER power management state
Description
Device not present or communication not established
Generation 1 communication rate negotiated
Generation 2 communication rate negotiated
Description
No device detected and Phy communication not established
Device presence detected but Phy communication not established
Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
running in a BIST loopback mode
Description
Attribute:
Size:
RO
32 bits
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