NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 18

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

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12.1.9 PMLT—Primary Master Latency Timer Register
12.1.10PCMD_BAR—Primary Command Block Base Address
12.1.11PCNL_BAR—Primary Control Block Base Address Register
12.1.12SCMD_BAR—Secondary Command Block Base Address
12.1.13SCNL_BAR—Secondary Control Block Base Address
12.1.14BAR — Legacy Bus Master Base Address Register
12.1.15ABAR/SIDPBA1 — AHCI Base Address Register/Serial
12.1.16SVID—Subsystem Vendor Identification Register
12.1.17SID—Subsystem Identification Register (SATA–D31:F2)............................. 474
12.1.18CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 474
12.1.19INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 475
12.1.20INT_PN—Interrupt Pin Register (SATA–D31:F2) ........................................ 475
12.1.21IDE_TIM — IDE Timing Register (SATA–D31:F2) ....................................... 475
12.1.22SIDETIM—Slave IDE Timing Register (SATA–D31:F2) ................................ 477
12.1.23SDMA_CNT—Synchronous DMA Control Register
12.1.24SDMA_TIM—Synchronous DMA Timing Register
12.1.25IDE_CONFIG—IDE I/O Configuration Register
12.1.26PID—PCI Power Management Capability Identification
12.1.27PC—PCI Power Management Capabilities Register
12.1.28PMCS—PCI Power Management Control and Status
12.1.29MSICI—Message Signaled Interrupt Capability Identification
12.1.30MSIMC—Message Signaled Interrupt Message Control
12.1.31MSIMA— Message Signaled Interrupt Message Address
12.1.32MSIMD—Message Signaled Interrupt Message
12.1.33MAP—Address Map Register (SATA–D31:F2)............................................. 486
12.1.34PCS—Port Control and Status Register
12.1.35SCLKCG—SATA Clock Gating Control Register........................................... 489
12.1.36SCLKGC—SATA Clock General Configuration Register................................. 490
12.1.37SIRI—SATA Indexed Registers Index Register........................................... 490
12.1.38STRD—SATA Indexed Register Data Register ............................................ 490
12.1.39STTT1—SATA Indexed Registers Index 00h
12.1.40SIR18—SATA Indexed Registers Index 18h
12.1.41STME—SATA Indexed Registers Index 1Ch
(SATA–D31:F2) .................................................................................... 471
Register (SATA–D31:F2)........................................................................ 471
(SATA–D31:F2) .................................................................................... 471
Register (IDE D31:F1) ........................................................................... 472
Register (IDE D31:F1) ........................................................................... 472
(SATA–D31:F2) .................................................................................... 473
ATA Index Data Pair Base Address (SATA–D31:F2).................................... 473
12.1.15.1When CC.SCC is not 01h .......................................................... 473
12.1.15.2When CC.SCC is 01h................................................................ 474
(SATA–D31:F2) .................................................................................... 474
(SATA–D31:F2) .................................................................................... 478
(SATA–D31:F2) .................................................................................... 478
(SATA–D31:F2) .................................................................................... 480
Register (SATA–D31:F2)........................................................................ 481
(SATA–D31:F2) .................................................................................... 482
Register (SATA–D31:F2)........................................................................ 482
(SATA–D31:F2) .................................................................................... 483
(SATA–D31:F2) .................................................................................... 483
(SATA–D31:F2) .................................................................................... 485
Data (SATA–D31:F2)............................................................................. 485
(SATA–D31:F2) .................................................................................... 487
(SATA TX Termination Test Register 1) .................................................... 492
(SATA Initialization Register 18h) ........................................................... 492
(SATA Test Mode Enable Register) .......................................................... 492
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