NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 455

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1) (Mobile Only)
11.1.18
11.1.19
11.1.20
Intel
®
ICH8 Family Datasheet
INTR_LN—Interrupt Line Register (IDE—D31:F1)
Address Offset:
Default Value:
INTR_PN—Interrupt Pin Register (IDE—D31:F1)
Address Offset:
Default Value:
IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)
Address Offset:
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
13:12
11:10
7:0
Bit
7:0
Bit
9:8
Bit
15
14
Interrupt Line (INT_LN) — R/W. This field is used to communicate to software the
interrupt line that the interrupt pin is connected to.
Interrupt Pin — RO. This reflects the value of D31IP.PIP (Chipset Config
Registers:Offset 3100h:bits 7:4).
IDE Decode Enable (IDE) — R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit 0)
in the Command register must be set in order for this bit to have any effect.
0 = Disable.
1 = Enables the ICH8M to decode the Command (1F0–1F7h) and Control (3F6h) Blocks.
This bit also effects the memory decode range for IDE Expansion.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determine the number
of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum
number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe
of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
3Ch
00h
3Dh
See Register Description
40
0000h
–
41h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
16 bits
8 bits
R/W
R/W
8 bits
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