NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 166

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Table 66.
5.13.5.1
166
Break Events (Mobile Only)
Slow C4 Exit (Mobile Only)
To eliminate the audible noise caused by aggressive voltage ramps when exiting C4
states at a regular, periodic frequency, the ICH8 supports a method to slow down the
voltage ramp at the processor VR for certain break events. If enabled for this behavior,
the ICH8 treats IRQ0 and IRQ8 as “slow” break events since both of these can be the
system timer tick interrupt. Rather than carefully tracking the interrupt and timer
configuration information to track the one correct interrupt, it was deemed acceptable
to simplify the logic and slow the break exit sequence for both interrupts. Other break
event sources invoke the normal exit timings.
The ICH8 indicates that a slow voltage ramp is desired by deasserting DPRSTP# (high)
and leaving DPRSLPVR asserted (high). The normal voltage ramp rate is communicated
by deasserting DPRSTP# (high) and deasserting DPRSLPVR (low).
The ICH8 waits an additional delay before starting the normal voltage ramp timer
during the C4 exit sequence. If a “fast” break event occurs during the additional, slow-
Exit time delay, the ICH8 quickly deasserts DPRSLPVR (low), thereby speeding up the
voltage ramp and reducing the delay to a value that is typically seen by the device in
the past. In the event that a fast break event and a slow break event occur together,
the fast flow is taken.
The ICH8 provides enable for Slow C4 Exit as well as a programmable delay time.
Any unmasked interrupt goes
active
Any internal event that cause an
NMI or SMI#
Any internal event that cause
INIT# to go active
Any bus master request
(internal, external or DMA, or
BMBUSY#) goes active and
BM_RLD=1 (D31:F0:Offset
PMBASE+04h: bit 1)
Processor Pending Break Event
Indication
Event
C2, C3, C4
C2, C3, C4
C2, C3, C4
C2, C3, C4
Breaks
C3, C4
from
IRQ[0:15] when using the 8259s, IRQ[0:23]
for I/O APIC. Since SCI is an interrupt, any SCI
will also be a break event.
Many possible sources
Could be indicated by the keyboard controller
via the RCIN input signal.
Need to wake up processor so it can do snoops
NOTE: If the PUME bit (D31:F0: Offset A9h:
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS,
Chipset Config Registers:Offset 3410h:bit 6)
bit 3) is set, then bus master activity
will NOT be treated as a break event.
Instead, there will be a return only to
the C2 state.
Comment
Intel
®
Functional Description
ICH8 Family Datasheet