NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 142

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

5.8.2.2
5.8.2.3
5.8.2.4
5.8.3
142
ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
ICW4
The final write in the sequence (ICW4) must be programmed for both controllers. At
the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in
an Intel Architecture-based system.
Operation Command Words (OCW)
These command words reprogram the Interrupt controller to operate in various
interrupt modes.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to
• For the slave controller, ICW3 is the slave identification code used during an
• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
• OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM),
cascade the slave controller. Within the ICH8, IRQ2 is used. Therefore, bit 2 of
ICW3 on the master controller is set to a 1, and the other bits are set to 0s.
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
and controls the EOI function.
and enables/disables polled interrupt mode.
Intel
®
Functional Description
ICH8 Family Datasheet