HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 94

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

pins. They can also drive a Darlington pair.
Table 5-7 details the port 3 registers.
Table 5-7. Port 3 Registers
Name
Port 3 data direction register
Port 3 data register
Port 3 Data Direction Register (P3DDR)—H’FFB4
Bit
Initial value
Read/Write
P3DDR is an 8-bit register that selects the direction of each pin in port 3. A pin functions as an
output pin if the corresponding bit in P3DDR is set to 1, and as an input pin if the bit is cleared to 0.
Port 3 Data Register (P3DR)—H’FFB6
Bit
Initial value
Read/Write
P3DR is an 8-bit register containing output data for pins P3
input pull-ups.
MOS Pull-Ups: Are available for input pins in mode 3. Software can turn on the MOS pull-up by
writing a 1 in P3DR, and turn it off by writing a 0. The pull-ups are automatically turned off for
output pins in mode 3, and for all pins in modes 1 and 2.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values in
P3DDR and P3DR are ignored.
Mode 3: In the single-chip mode, port 3 can be used as a general-purpose input/output port, or a
parallel-handshaking input or output port.
P3
R/W
7
P3
W
DDR P3
7
0
7
0
7
R/W
6
P3
W
DDR P3
6
0
6
0
Abbreviation
P3DDR
P3DR
6
R/W
5
P3
W
DDR P3
5
0
5
0
5
R/W
85
Read/Write
W
R/W
4
P3
W
DDR P3
4
0
4
0
4
R/W
3
P3
7
W
DDR P3
3
0
3
0
to P3
3
Initial value
H’FF
H’00
0
in mode 3, and controlling their
R/W
2
P3
W
DDR P3
2
0
2
0
2
R/W
1
P3
W
DDR P3
1
0
1
0
1
R/W
0
P3
W
DDR
0
0
0
0
Address
H’FFB4
H’FFB6
0