HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 170

IC H8 MCU OTP 32K 64DIP

HD6473258P10

Manufacturer Part Number
HD6473258P10
Description
IC H8 MCU OTP 32K 64DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet

Specifications of HD6473258P10

Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Peripherals
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473258P10
Manufacturer:
EXEL
Quantity:
6 218
Part Number:
HD6473258P10
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD6473258P10
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
600
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
1 200
Part Number:
HD6473258P10V
Manufacturer:
HITACHI/日立
Quantity:
20 000
8.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 8-3 lists information about these interrupts.
Table 8-3. 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
8.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared
(2) In the TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
when its value matches the constant in TCORA.
match A and to 0 on compare-match B.
OVF
Ø
Description
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
Figure 8-11. Clearing of Overflow Flag
When cycle: CPU writes "0" in OVF
T
1
T
163
2
T
3
Priority
High
Low

Related parts for HD6473258P10