HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 199

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

If the last bit of the next byte is received while the RDRF bit is still set to 1, an overrun error
occurs. The error is handled as described under “Data Reception” above. The overrun error does
not affect the transmit section of the SCI, which continues to transmit normally.
9.4 Interrupts
The SCI can request three types of interrupts: transmit-end (TXI), receive-end (RXI), and receive-
error (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the SCR.
Independent signals are sent to the interrupt controller for each type of interrupt. The transmit-end
and receive-end interrupt request signals are obtained from the TDRE and RDRF flags. The
receive-error interrupt request signal is the logical OR of the three error flags: overrun error
(ORER), framing error (FER), and parity error (PER). Table 9-9 lists information about these
interrupts.
Data transmitting and receiving start when the TDRE bit in the SSR is cleared to 0.
Data are sent and received in synchronization with eight clock pulses.
First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty,
so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested.
If continuous data transmission is desired, software must read the TDRE bit in the SSR, write
the next transmit data in the TDR, then clear the TDRE bit to 0.
If the TDRE bit is not cleared to 0 by the time the SCI finishes sending the current byte from
the TSR, the TxD pin continues to output the value of last bit of the previous data.
In the receiving section, when 8 bits of data have been received they are transferred from the
RSR to the RDR and the RDRF bit in the SSR is set to 1. If the RIE bit is set to 1, a receive-
end interrupt (RXI) is requested.
To clear the RDRF bit software should read the RDRF bit in the SSR, read the data in the RDR,
then write a 0 in the RDRF bit.
For continuous data reception, software should clear the RDRF bit to 0 before reception of the
next 8 bits is completed.
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