HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 91

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Pins of port 2 can drive a single TTL load and a 90-pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes or a Darlington pair.
Table 5-5 details the port 2 registers.
Table 5-5. Port 2 Registers
Name
Port 2 data direction register
Port 2 data register
Port 2 Data Direction Register (P2DDR)—H’FFB1
Bit
Mode 1
Modes 2 and 3
P2DDR is an 8-bit register that selects the direction of each pin in port 2. A pin functions as an
output pin if the corresponding bit in P2DDR is set to 1, and as an input pin if the bit is cleared to 0.
Port 2 Data Register (P2DR)—H’FFB3
Bit
Initial value
Read/Write
P2DR is an 8-bit register containing output data for pins P2
ups.
MOS Pull-Ups: Are available for input pins in modes 2 and 3. Software can turn on the MOS pull-
up by writing a 1 in P2DR, and turn it off by writing a 0. The pull-ups are automatically turned off
for output pins in modes 2 and 3, and for all pins in mode 1.
Initial value
Read/Write
Initial value
Read/Write
P2
R/W
7
P2
—
W
DDR P2
7
1
0
7
0
7
R/W
6
P2
—
W
DDR P2
6
1
0
6
0
Abbreviation
P2DDR
P2DR
6
R/W
5
P2
—
W
DDR P2
5
1
0
5
0
5
R/W
82
Read/Write
W
R/W
4
P2
—
W
DDR P2
4
1
0
4
0
4
R/W
3
P2
7
—
W
DDR P2
3
1
0
3
0
to P2
3
Initial value
H’FF (mode 1)
H’00 (modes 2 and 3)
H’00
0
, and controlling their input pull-
R/W
2
P2
—
W
DDR P2
2
1
0
2
0
2
R/W
1
P2
—
W
DDR P2
1
1
0
1
0
1
R/W
0
P2
—
W
DDR
0
1
0
0
0
Address
H’FFB1
H’FFB3
0