HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 140

IC H8 MCU OTP 32K 64DIP

HD6473258P10

Manufacturer Part Number
HD6473258P10
Description
IC H8 MCU OTP 32K 64DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet

Specifications of HD6473258P10

Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Peripherals
-

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Bit 4
OVF
0
1
Bit 3 – Output Level B (OLVLB): Selects the logic level output at the FTOB pin when the FRC
and OCRB values match.
Bit 3
OLVLB
0
1
Bit 2 – Output Level A (OLVLA): Selects the logic level output at the FTOA pin when the FRC
and OCRA values match.
Bit 2
OLVLA
0
1
Bit 1 – Input Edge Select (IEDG): Selects the rising or falling edge of the input capture signal
(FTI).
Bit 1
IEDG
0
1
Bit 0 – Counter Clear A (CCLRA): Selects whether to clear the FRC at compare-match A (when
the FRC and OCRA values match).
Bit 0
CCLRA
0
1
Description
To clear OVF, the CPU must read OVF after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC changes from H’FFFF to H’0000.
Description
A 0 logic level is output for compare-match B.
A 1 logic level is output for compare-match B.
Description
A 0 logic level is output for compare-match A.
A 1 logic level is output for compare-match A.
Description
FRC contents are transferred to ICR on the falling edge of FTI. (Initial value)
FRC contents are transferred to ICR on the rising edge of FTI.
Description
The FRC is not cleared.
The FRC is cleared at compare-match A.
132
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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