HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 109

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Table 5-12. Port 6 Pin Functions
Usage
I/O port
Timer/interrupt FTCI
See section 4, Exception Handling and section 7, Free-Running Timer Module for details of the
free-running timer and interrupts.
Pins of port 6 can drive a single TTL load and a 90-pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-13 details the port 6 registers.
Table 5-13. Port 6 Registers
Name
Port 6 data direction register
Port 6 data register
Port 6 Data Direction Register (P6DDR)—H’FFB9
Bit
Initial value
Read/Write
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an
output pin if the corresponding bit in P6DDR is set to 1, and as an input pin if the bit is cleared to 0.
Port 6 Data Register (P6DR)—H’FFBB
Bit
Initial value
Read/Write
P6DR is an 8-bit register containing output data for pins P6
ups. When the CPU reads P6DR, for output pins (P6DDR = 1) it reads the value in the P6DR latch,
but for input pins (P6DDR = 0), it obtains the logic level directly from the pin, bypassing the P6DR
latch. This also applies to pins used for input and output of timer and interrupt signals.
Pin functions (Modes 1 to 3)
P6
—
—
—
—
7
1
7
0
0
P6
P6
FTOA
R/W
6
P6
W
DDR P6
6
0
6
0
1
Abbreviation
P6DDR
P6DR
6
P6
FTOB
R/W
5
P6
W
DDR P6
5
0
5
0
2
5
P6
FTI
100
R/W
Read/Write
W
R/W
4
P6
W
DDR P6
4
0
4
0
3
4
P6
IRQ
R/W
3
P6
6
W
DDR P6
3
0
3
0
4
to P6
3
0
Initial value
H’80
H’80
0
, and controlling their input pull-
P6
IRQ
R/W
2
P6
W
DDR P6
2
0
2
0
5
2
1
P6
IRQ
R/W
1
P6
W
DDR P6
1
0
1
0
6
1
2
R/W
0
P6
W
DDR
0
0
0
0
Address
H’FFB9
H’FFBB
0