HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 35

IC H8 MCU OTP 32K 64DIP

HD6473258P10

Manufacturer Part Number
HD6473258P10
Description
IC H8 MCU OTP 32K 64DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet

Specifications of HD6473258P10

Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Peripherals
-

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2.4.2 System Control Register (SYSCR)—H’FFC4
By setting or clearing bit 0 of the system control register, software can enable or disable the on-chip
RAM.
The other bits in the system control register concern the software standby mode and the valid edge
of the NMI signal. These bits will be described in section 4, Exception Handling and section 12,
Power-Down State.
Bit
Initial value
Read/Write
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. When the on-chip
RAM is disabled, accesses to the corresponding addresses are directed off-chip.
The RAME bit is initialized to 1 by a reset, enabling the on-chip RAM. The setting of the RAME
bit is not altered in the sleep mode or software standby mode. It should be cleared to 0 before
entering the hardware standby mode. See section 12, Power-Down State.
Bit 0
RAME
Coding Example: To disable the on-chip RAM:
0
1
BCLR #0, @H’FFC4
Description
The on-chip RAM is disabled.
The on-chip RAM is enabled.
SSBY
R/W
7
0
STS2
R/W
6
0
STS1
R/W
5
0
STS0
R/W
25
4
0
3
1
NMIEG
R/W
2
0
(Initial state)
1
1
RAME
R/W
0
1

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