HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 182

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

9.2.6 Serial Control Register (SCR) – H’FFDA
Bit
Initial value
Read/Write
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is
initialized to H’0C at a reset and in the standby modes.
Bit 7 – Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to 1.
Bit 7
TIE
Bit 6 – Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to 1, and the receive error interrupt (ERI) requested when the overrun error bit (ORER), framing
error bit (FER), or parity error bit (PER) is set to 1.
Bit 6
RIE
Bit 5 – Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE
0
1
0
1
0
1
Description
The transmit function is disabled.
The TxD pin can be used for general-purpose I/O.
The transmit function is enabled.
The TxD pin is used for output.
Description
The transmit-end interrupt request (TXI) is disabled.
The transmit-end interrupt request (TXI) is enabled.
Description
The receive-end interrupt (RXI) request is disabled.
The receive-end interrupt (RXI) request is enabled.
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
175
R/W
RE
4
0
—
—
3
1
—
—
2
1
CKE1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKE0
R/W
0
0