HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 194

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

* A frame is the data for one character, including the start bit and stop bit(s).
• Data Reception: The procedure for receiving data is as follows.
When a frame is not received correctly, a receive error occurs. There are three types of receive
errors, listed in table 9-8.
The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated
format as follows.
i) Start bit (one 0 bit).
ii) Transmit data (seven or eight bits, starting from bit 0)
iii) Parity bit (odd or even parity bit, or no parity bit)
iv) Stop bit (one or two consecutive 1 bits)
Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit
is set to 1.
If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested.
When the transmit function is enabled but the TDR is empty (TDRE = 1), the output at the TxD
pin is held at 1 until the TDRE bit is cleared to 0.
Set up the desired receiving conditions in the SMR, SCR, and BRR.
Set the RE bit in the SCR to 1.
The RxD pin is automatically be switched to input and the SCI is ready to receive data.
The SCI synchronizes with the incoming data by detecting the start bit, and places the received
bits in the RSR. At the end of the data, the SCI checks that the stop bit is 1.
When a complete frame has been received, the SCI transfers the received data from the RSR to
the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the
RDR is cleared to 0.
At the same time, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-
end interrupt (RXI) is requested.
The RDRF bit is cleared to 0 when software reads the SSR, then writes a 0 in the RDRF bit.
The RDR is then ready to receive the next character from the RSR.
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