HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 88

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Table 5-3 details the port 1 registers.
Table 5-3. Port 1 Registers
Name
Port 1 data direction register
Port 1 data register
Port 1 Data Direction Register (P1DDR)—H’FFB0
Bit
Mode 1
Modes 2 and 3
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an
output pin if the corresponding bit in P1DDR is set to 1, and as an input pin if the bit is cleared to 0.
Port 1 Data Register (P1DR)—H’FFB2
Bit
Initial value
Read/Write
P1DR is an 8-bit register containing output data for pins P1
ups.
MOS Pull-Ups: Are available for input pins in modes 2 and 3. Software can turn on the MOS pull-
up by writing a 1 in P1DR, and turn it off by writing a 0. The pull-ups are automatically turned off
for output pins in modes 2 and 3, and for all pins in mode 1.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for
address output. The port 1 data direction register is unwritable. All bits in P1DDR are automatically
set to 1 and cannot be cleared to 0.
Initial value
Read/Write
Initial value
Read/Write
P1
R/W
7
P1
—
W
DDR P1
7
1
0
7
0
7
R/W
6
P1
—
W
DDR P1
6
1
0
6
0
Abbreviation
P1DDR
P1DR
6
R/W
5
P1
—
W
DDR P1
5
1
0
5
0
5
R/W
79
Read/Write
W
R/W
4
P1
—
W
DDR P1
4
1
0
4
0
4
R/W
3
P1
7
—
W
DDR P1
3
1
0
3
0
to P1
3
Initial value
H’FF (mode 1)
H’00 (modes 2 and 3)
H’00
0
, and controlling their input pull-
R/W
2
P1
—
W
DDR P1
2
1
0
2
0
2
R/W
1
P1
—
W
DDR P1
1
1
0
1
0
1
R/W
0
P1
—
W
DDR
0
1
0
0
0
Address
H’FFB0
H’FFB2
0