HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 40

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

3.3 Addressing Modes
The H8/325 supports eight addressing modes. Each instruction uses a subset of these addressing
modes.
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
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(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H’FFxx.
The upper 8 bits are assumed to be 1, so the possible address range is H’FF00 to H’FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
The @–Rn mode is used with MOV instructions that store register contents to memory.
Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
Register Indirect with Pre-Decrement—@–Rn
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the
decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For
MOV.W, the original contents of the 16-bit general register must be even.
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