HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 7

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

7.5
7.6
7.7
7.8
Section 8. 8-Bit Timers
8.1
8.2
8.3
8.4
8.5
8.6
Section 9. Serial Communication Interface
9.1
9.2
7.4.6
Interrupts............................................................................................................................... 142
Noise Canceler...................................................................................................................... 142
Sample Application............................................................................................................... 144
Application Notes ................................................................................................................. 145
Overview............................................................................................................................... 151
8.1.1
8.1.2
8.1.3
8.1.4
Register Descriptions............................................................................................................ 153
8.2.1
8.2.2
8.2.3
8.2.4
Operation .............................................................................................................................. 158
8.3.1
8.3.2
8.3.3
8.3.4
Interrupts............................................................................................................................... 163
Sample Application............................................................................................................... 163
Application Notes ................................................................................................................. 164
Overview............................................................................................................................... 169
9.1.1
9.1.2
9.1.3
9.1.4
Register Descriptions............................................................................................................ 171
9.2.1
9.2.2
9.2.3
9.2.4
Setting of FRC Overflow Flag (OVF)..................................................................... 141
Features.................................................................................................................... 151
Block Diagram......................................................................................................... 151
Input and Output Pins .............................................................................................. 152
Register Configuration ............................................................................................ 153
Timer Counter (TCNT) – H’FFC8 (TMR0), H’FFD0 (TMR1) .............................. 153
Time Constant Registers A and B (TCORA and TCORB) –
H’FFCA and H’FFCB (TMR0), H’FFD2 and H’FFD3 (TMR1)............................ 154
Timer Control Register (TCR) – H’FFC8 (TMR0), H’FFD0 (TMR1) ................... 154
Timer Control/Status Register (TCSR) – H’FFC9 (TMR0), H’FFD1 (TMR1)...... 156
TCNT Incrementation Timing................................................................................. 158
Compare Match Timing........................................................................................... 159
External Reset of TCNT .......................................................................................... 161
Setting of TCSR Overflow Flag .............................................................................. 162
Features.................................................................................................................... 169
Block Diagram......................................................................................................... 170
Input and Output Pins .............................................................................................. 170
Register Configuration ............................................................................................ 171
Receive Shift Register (RSR) .................................................................................. 171
Receive Data Register (RDR) – H’FFDD ............................................................... 172
Transmit Shift Register (TSR)................................................................................. 172
Transmit Data Register (TDR) – H’FFDB .............................................................. 172
......................................................................................................... 151
iv
..................................................................... 169